1. Field of the Invention
The present invention generally relates to a nonvolatile ferroelectric memory device, and more specifically, to a nonvolatile ferroelectric memory device having a multi bit line structure where the main bit line is shared by a plurality of sub bit lines to improve a cell array structure, thereby reducing the number of main bit lines, and layout area of the memory and making the layout process easier.
2. Description of the Prior Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) has a data processing speed as fast as a Dynamic Random Access Memory (hereinafter, referred to as ‘DRAM’) and conserves data even after the power is turned off.
The FeRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
FIG. 1 is a circuit diagram illustrating a cell array block having a conventional multi bit line structure.
In each sub cell array, main bit lines MBL are connected one by one to the sub bit lines SBL in parallel.
When a sub bit line selecting signal SBSW1 is activated, corresponding NMOS transistors N5 and N10 are turned on, so that loads of main bit lines MBL<0> and MBL<1> are burdened at levels of one corresponding sub bit line SBL<0> or SBL<1>. Also, when a sub bit line pull-down signal SBPD is activated, NMOS transistors N3 and N8 are turned on, so that the sub bit line SBL<0> or SBL<1> is regulated at a ground voltage level.
A sub bit line pull-up signal SBPU is to regulate power which is supplied to the sub bit lines SBL<0> and SBL<1>, and sub bit line selecting signals SBSW2_L and SBSW2_R are to regulate signal flow between the sub bit line pull-up signal SBPU and the sub bit lines SBL<0> and SBL<1>, respectively.
For example, when a high voltage is required to be generated in a low voltage, a voltage higher than a power voltage VCC is supplied as the sub bit line pull-up signal SBPU. Then, when the sub bit line selecting signal SBSW2_L is activated, a NMOS transistor N4 is turned on, so that the high voltage is supplied to the sub bit line SBL<0>. A plurality of cells each comprising a NMOS transistor and a ferroelectric capacitor are connected to the sub bit line SBL<0> and SBL<1>, respectively.
A NMOS transistor N1 is connected between a ground voltage terminal and a NMOS transistor N2, and a NMOS transistor N6 is connected between the ground voltage terminal and a NMOS transistor N7. Each of the NMOS transistors N1 and N6 receives a main bit line pull-down signal MBPD. The NMOS transistor N2, connected between the NMOS transistor N1 and the main bit line MBL<0>, has a gate connected to the sub bit line SBL<0>. The NMOS transistor N7, connected between the NMOS transistor N6 and the main bit line MBL<1>, has a gate connected to the sub bit line SBL<1>. When the main bit line pull-down signal MBPD is activated, each of the NMOS transistors N2 and N7 regulates the amount of current leaked from the main bit line MBL<0> and MBL<1> depending on data values of the sub bit lines SBL<0> and SBL<1>, thereby inducing sensing voltages of the main bit lines MBL<0> and MBL<1>. That is, voltages of different levels applied to the sub bit lines SBL<0> and SBL<1> vary channel resistance of the NMOS transistors N2 and N7 depending on cell data, thereby regulating the sensing voltages of the main bit lines MBL<0> and MBL<1> to have different levels.
A sense amplifier senses and amplifies a voltage difference of the main bit lines which is generated through the above-described principle.
FIG. 2 is a cross-sectional diagram illustrating a main bit line and a sub bit line which have the structure of FIG. 1.
Main bit lines MBL<0>˜MBL<3> are connected one by one to sub bit lines SBL<0>˜SBL<3> to be paired off.
In this multi bit line structure, the sub bit line SBL is formed of poly silicon or tungsten metal. On the other hand, the main bit line MBL is formed of Al or Cu. However, since thick metal is used to reduce resistance, the width and space of the metal become larger than those of other layers.
As the size of the cell becomes smaller, the space between the main bit lines becomes also smaller. As a result, the technology of securing a space for formation of main bit lines is required.